1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly relates to a semiconductor memory device including a vertical transistor using a silicon pillar and a method of manufacturing the semiconductor memory device.
2. Description of Related Art
In recent years, the integration enhancement of semiconductor memory devices has been mainly achieved by downscaling the transistor size. However, the downscaling of the transistor size is coming close to its limit, and if the transistor size is reduced even more, it may cause a malfunction of the transistor due to a short channel effect or the like.
As a measure to fundamentally solve such a problem, a method of forming transistors in a three-dimensional manner by three-dimensionally processing a semiconductor substrate has been proposed. In particular, a three-dimensional transistor that uses a silicon pillar that extends in a vertical direction with respect to a main plane of the semiconductor substrate as a channel has an advantage in that its occupation area is small, a large drain current can be obtained by a complete depletion, and it is possible to realize the close-packed layout of 4F2 (where F is the minimum feature size) (see Japanese Patent Application Laid-open Nos. 2008-288391, 2008-300623, 2008-311641, and 2009-010366).
There are various types of specific configurations of vertical transistors using silicon pillars, and according to one of them, bit lines are provided between a large number of silicon pillars arranged in a matrix. While each of the bit lines is electrically connected to a top end or a bottom end of each of adjacent silicon pillars, the bit line is connected to only silicon pillars on one side in an extending direction of the bit line. Specifically, such connection is realized by providing an opening at a part of an oxide film for insulation that covers the bit line.
Because the vertical transistor using silicon pillars is for realizing a close-packed layout of 4F2, the oxide film for insulation that covers the bit line is made considerably thin. Therefore, to form the opening, a processing precision of F value or lower is required. Accordingly, it is very difficult to form the opening.